This application is based upon and claims the benefits of priority from the prior Japanese Patent Application No. 2001-076973, filed Mar. 16, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to an offset compensation circuit (or offset adjustor) for compensating the DC offset of the output signal of an analog signal processing circuit. Such an offset compensation circuit can suitably be used for a circuit where the DC offset of the output significantly affects the operation and the performance of the analog front-end signal processing LSI of a CD player or a DVD player.
2. Description of the Related Art
Generally, the DC input offset of a stand-alone OP amplifier is produced by mismatches among the performances of the transistors constituting the differential input stage of the amplifier. Causes of such mismatches among the performances of transistors are found mostly in the transistor manufacturing process. Particularly, in the case of MOS transistors, it is highly difficult to reduce the problem simply by improving the manufacturing process.
In view of this fact, methods for compensating (or adjusting) the DC input offset by means of a specifically devised circuit have been developed. Such circuits are marketed and include ICL7650 (trade name, available from INTERSIL), MAX430, 432 (trade names, available from Maxim) and TSC911, 913, 914 (trade names, available from TSC).
FIG. 1 of the accompanying drawings shows a schematic circuit diagram of a conventional offset compensation circuit for compensating the DC input offset of a stand-alone OP amplifier. The circuit is designed to compensate the DC input offset of an OP amplifier 10 comprising PMOS (P-channel type MOS) transistors MP1, MP2 and NMOS (N-channel type MOS) transistors MN1, MN2, MN4. The OP amplifier 10 receives non-inverted input signal VPin, inverted input signal VMin and bias voltage VBIAS as inputs and outputs output signal VOUT. In an OP amplifier 10 having such a configuration, the mismatch among the performance of the PMOS transistors MP1, MP2 and those of the NMOS transistors MN1, MN2 can give rise to a DC input offset.
The offset compensation circuit is so formed as to comprise a PMOS transistor MP3, an NMOS transistor MN3, switches SW1, SW2, an amplifier 11, a reference voltage generating circuit 12 and capacitors (or capacitive elements) C1, C2.
The circuit as shown in FIG. 1 is referred to as chopper-stabilized amplifier. A chopper-stabilized amplifier comprises an offset detection stage 13 formed by arranging transistors MP3, MN3 for detecting an DC offset and annexed to the ordinary differential stage formed by arranging transistors MP1, MP2 and transistors MN1, MN2.
The offset compensating effect of the offset compensation circuit is realized by alternately connecting the two switches SW1, SW2 to swA side and swB side in FIG. 1. More specifically, when the switches SW1, SW2 are connected to the swA side, a same inverted input signal VMin is input to both of the transistors MN1, MN2. Then, the back gate potential of the transistor MP1 is controlled by the amplifier 11 in such a way that the output level of the transistors MP3 and MN3 are the same level of the reference voltage Vr output from the reference voltage generating circuit 12. When the control session is completed, the output level of the transistors MP1 and MN1 are brought to the level of the reference voltage Vr that is the same output level of the transistors MP3 and MN3.
When, on the other hand, the switches SW1, SW2 are connected to the swB side, a same non-inverted input signal VPin is input to both of the transistors MN2, MN3. Then, the back gate potential of the transistor MP2 is controlled by the amplifier 11 in such a way that the output level of the transistors MP3 and MN3 are the same level of the reference voltage Vr. When the control session is completed, the output level of the transistors MP2 and MN2 are brought to the level of the reference voltage Vr that is the same output level of the transistors MP3 and MN3.
By repeating these two sessions alternately, the output level of the transistors MP1 and MN1 and that of the transistors MP2 and MN2 are controlled to become equal to the same reference voltage Vr. As a result, the error voltages due to the respective DC input offsets are absorbed as the difference of the control voltages for controlling the back gate potentials of the transistors MP1 and MP2. In this way, the respective DC input offsets become compensated.
The capacitors C1 and C2 are used to hold the respective control voltages because the respective back gate terminals of the transistors MP1, MP2 are in a high impedance state when the back gate potentials are not controlled.
However, the above described chopper-stabilized amplifier requires, as annex circuits, a detection stage (transistors MP3 and MN3) for detecting the DC input offsets of the transistors MP1 and MP2, a back gate control amplifier 11, a reference voltage generating circuit 12, capacitors for holding the respective control voltages, and a clock generation circuit for generating a chopping clock. Additionally, since a chopping clock produces switching noise, it cannot be used with a high frequency zone and hence the capacitors C1 and C2 for holding the respective control voltages are inevitably required to have a large capacitance. Then, as a matter of course, there arises a problem of an increased chip size to the LSI.
Meanwhile, practical applications of amplifiers of the type under consideration include analog front-end signal processing LSIs to be used for CD players and DVD players. FIG. 2 shows a typically analog signal processing circuit realized by using such an amplifier. The circuit comprises op amplifiers 14 through 17, resistors (or resistive elements) R1 through R9, a variable resistor RV and capacitors C3 through C7.
When chopper-stabilized amplifiers are used in such a circuit, the circuit needs as many offset compensation circuits as the number of the amplifiers, although a clock generation circuit for generating a chopping clock may be commonly used. It is not unusual that an LSI is realized by using several ten such amplifiers in this field of application. Then, the circuit comprising chopper-stabilized amplifiers will inevitably show large dimensions. This dimensional problem becomes a serious one particularly when analog front-end signal processing LSIs are realized by using MOS transistors.
Beside the dimensional problem, the problem of switching noise produced by the chopping clock also requires consideration and entails cumbersome operations including the selection of the frequency of the chopping clock. While it is possible to reduce the adverse effect of switching noise, switching noise itself cannot be eliminated completely.
Furthermore, when the frequency of the input signal and the frequency of the chopping lock are close to each other, there arises a problem of mutual modulation where the input signal is modulated by the frequency of the chopping clock. This means that the frequency zone available to input signals is limited to by turn limit the scope of application of OP amplifiers.
According to an aspect of the present invention, there is provided an offset compensation circuit comprising; an analog/digital converter configured to measure a DC level of an inverting type analog output buffer in an analog signal processing circuit and convert an analog signal into a digital signal; a digital/analog converter configured to receive the digital signal output from the analog/digital converter as input and convert the digital signal into an analog signal; an attenuator configured to receive the analog signal output from the digital/analog converter as input and attenuate an amplitude of the analog signal; and an analog adder configured to receive the output signal of the attenuator and the output signal of the analog signal processing circuit as inputs, add the output signals and supply a sum signal as input signal to the inverting type analog output buffer.
According to another aspect of the invention, there is provided an offset compensation circuit comprising: an analog/digital converter configured to measure a DC level of a non-inverting type analog output buffer in an analog signal processing circuit and convert an analog signal into a digital signal; a digital/analog converter configured to receive the digital signal output from the analog/digital converter as input and convert the digital signal into an analog signal; an attenuator configured to receive the analog signal output from the digital/analog converter as input and attenuate an amplitude of the analog signal; and an analog subtracter configured to receive the output signal of the attenuator and the output signal of the analog signal processing circuit as inputs, subtract the output signal from the attenuator from the output signal from the analog signal processing circuit and supply a difference signal as input signal to the inverting type analog output buffer.
According to still another aspect of the present invention, there is provided an offset compensation circuit comprising: an analog/digital converter configured to measure a DC level of a non-inverting type analog output buffer in an analog signal processing circuit and convert an analog signal into a digital signal; a digital/analog converter configured to receive the digital signal output from the analog/digital converter as input and convert the digital signal into an analog signal; and an analog subtracter configured to receive the output signal of the digital/analog converter and the output signal of the analog signal processing circuit as inputs, subtract the output signal from the digital/analog converter from the output signal from the analog signal processing circuit and supply a difference signal as input signal to the inverting type analog output buffer.
According to still another aspect of the present invention, there is provided an offset compensation circuit comprising: an analog/digital converter configured to measure a DC level of an analog output buffer in an analog signal processing circuit and convert an analog signal into a digital signal; and first and second register circuits configured to receive and hold the digital signal output from the analog/digital converter; wherein the digital signal held by the first register circuit is input to the analog signal processing circuit and used for analog offset-compensation, and the digital signal held by the second register circuit is input to a digital signal processing circuit and used for digital offset-compensation.
According to still another aspect of the present invention, there is provided a semiconductor integrated circuit device provided with an analog signal processing circuit comprising an offset compensation circuit arranged at an output section of the analog signal processing circuit; the offset compensation circuit including: an analog/digital converter configured to measure a DC level of an inverting type analog output buffer in an analog signal processing circuit and convert an analog signal into a digital signal; a digital/analog converter configured to receive the digital signal output from the analog/digital converter as input and convert the digital signal into an analog signal; an attenuator configured to receive the analog signal output from the digital/analog converter as input and attenuate an amplitude of the analog signal; and an analog adder configured to receive the output signal of the attenuator and the output signal of the analog signal processing circuit as inputs, add the output signals and supply a sum signal as input signal to the inverting type analog output buffer.
According to still another aspect of the present invention, there is provided a semiconductor integrated circuit device provided with an analog signal processing circuit comprising an offset compensation circuit arranged at an output section of the analog signal processing circuit; the offset compensation circuit including: an analog/digital converter configured to measure a DC level of a non-inverting type analog output buffer in an analog signal processing circuit and convert an analog signal into a digital signal; a digital/analog converter configured to receive the digital signal output from the analog/digital converter as input and convert the digital signal into an analog signal; an attenuator configured to receive the analog signal output from the digital/analog converter as input and attenuate an amplitude of the analog signal; and an analog subtracter configured to receive the output signal of the attenuator and the output signal of the analog signal processing circuit as inputs, subtract the output signal from the attenuator from the output signal from the analog signal processing circuit and supply a difference signal as input signal to the inverting type analog output buffer.
According to still another aspect of the present invention, there is provided a semiconductor integrated circuit device provided with an analog signal processing circuit comprising an offset compensation circuit arranged at an output section of the analog signal processing circuit; the offset compensation circuit including: an analog/digital converter configured to measure a DC level of a non-inverting type analog output buffer in an analog signal processing circuit and convert an analog signal into a digital signal; a digital/analog converter configured to receive the digital signal output from the analog/digital converter as input and convert the digital signal into an analog signal; and an analog subtracter configured to receive the output signal of the digital/analog converter and the output signal of the analog signal processing circuit as inputs, subtract the output signal from the digital/analog converter from the output signal from the analog signal processing circuit and supply a difference signal as input signal to the inverting type analog output buffer.
According to still another aspect of the present invention, there is provided a semiconductor integrated circuit device provided with an analog signal processing circuit comprising an offset compensation circuit arranged at an output section of the analog signal processing circuit; the offset compensation circuit including: an analog/digital converter configured to measure a DC level of an analog output buffer in an analog signal processing circuit and convert an analog signal into a digital signal; and first and second register circuits configured to receive and hold the digital signal output from the analog/digital converter, wherein the digital signal held by the first register circuit is input to the analog signal processing circuit and used for analog offset-compensation, and the digital signal held by the second register circuit is input to a digital signal processing circuit and used for digital offset-compensation.
According to still another aspect of the present invention, there is provided an offset compensation method comprising: detecting a DC output offset of an inverting type analog output buffer in an analog signal processing circuit and converting the DC output offset into a digital signal; converting the detected DC output offset level into an analog signal level; attenuating the analog signal level produced by the conversion by an extent equal to the gain of the analog output buffer; adding the attenuated analog signal and the output signal of the analog signal processing circuit and supplying a sum signal to the analog output; and obtaining an output signal from the analog output buffer.
According to still another aspect of the present invention, there is provided an offset compensation method comprising; detecting a DC output offset of a non-inverting type analog output buffer in an analog signal processing circuit and converting the DC output offset into a digital signal; converting the detected DC output offset level into an analog signal level; attenuating the analog signal level produced by the conversion by an extent equal to the gain of the analog output buffer; subtracting the attenuated analog signal from the output signal of the analog signal processing circuit and supplying a difference signal to the analog output; and obtaining an output signal from the analog output buffer.
According to still another aspect of the present invention, there is provided an offset compensation method comprising; detecting a DC output offset of a non-inverting type analog output buffer in an analog signal processing circuit and converting the DC output offset into a digital signal; converting the detected DC output offset level into an analog signal level; subtracting the analog signal level from the output signal of the analog signal processing circuit and supplying a difference signal to the analog output; and obtaining an output signal from the analog output buffer.
According to still another aspect of the present invention, there is provided an offset compensation method comprising: detecting a DC output offset of an analog output buffer in an analog signal processing circuit and converting the DC output offset into a digital signal; holding the detected digital signal in a first register circuit; feeding back the digital signal held in the first register circuit to the analog signal processing circuit and analog compensation the offset; detecting the DC output offset level in the analog signal processing circuit and converting the DC output offset again into a digital signal; holding the detected digital signal in a second register; and inputting the digital signal held in the second register into a digital signal processing circuit and digital compensation the offset.